With the diminution and diverse functions of the electronic product, the threshold voltage and current consumption of the memory therein are also getting lower. For a non-volatile memory, the material used and the storage method are both aiming at enhancing endurance times of reading, reducing the time of data writing/reading/erasing, prolonging the data retention time and reducing power consumption during operation.
Please refer to FIG. 1(a), which shows a conventional EEPROM during writing. The EEPROM 10 has a logical state. For example, the structure of EEPROM 10 with a NMOS includes a p-type substrate 11, electric charges 15 and a gate 14. The p-type substrate 11 includes a source S and a drain D, and the gate 14 includes a dielectric layer 12 and a floating gate 13. During writing of the EEPROM 10, the source S and drain D are connected to the ground GND, and a positive voltage of 20 V is applied to the gate 14. The tunneling effect is induced by the vertical electric field, which leads to the electrons 15 tunneling through the dielectric layer 12 into the floating gate 13 and being trapped in the floating gate 13.
Please refer to FIG. 1(b), which shows a conventional EEPROM during erasing. For example, during the erasing of the EEPROM structure with a NMOS, a positive voltage of 20 V is applied to the drain D, and the gate 14 is connected to the ground GND. The high electric field induces the tunneling effect, which leads to the electrons 15 tunneling from the floating gate 13 into the drain D, so that the electrons 15 in the floating gate 13 are removed. The logical state can be changed after the above-mentioned method of writing and erasing. The disadvantage of using the floating gate 13 to trap the electric charges 15 is that once there are defects in the dielectric layer 12 around the floating gate 13, a part of the electric charges 15 will be lost. Due to the advancement of processes and diminution of elements, the thickness of the dielectric layer 12 is getting thinner. Therefore, another new structure is proposed.
Please refer to FIG. 2, which shows the structure of a conventional SONOS memory. The SONOS memory 30 includes a first substrate 36 and a gate 34, wherein the gate 34 includes a first dielectric layer 35, a nitride layer 31, a blocking oxide layer 32 and a polysilicon layer 33. The function of the nitride layer 31 is similar to that of the floating gate 13, which are both used for trapping electrons. The difference between the nitride layer 31 and the floating gate 13 is that the nitride layer 31 includes many films of discrete electrons storage areas. Besides, the blocking oxide layer 32 on the nitride layer 31 can prevent the electrons trapped by the nitride layer 31 from gate induced leakage. Moreover, the blocking oxide layer 32 on the nitride layer 31 can also reduce the writing voltage and enhance the endurance and reliability of the SONOS memory 30.
A new memory technology is proposed in the essay “Innovating SOI memory devices based on floating-body effects” by M. Bawedin et al., which stores the amount of carriers in the floating body to affect the threshold voltage of the device and modulate the magnitude of the drain current.
Please refer to FIG. 3(a), which shows the floating body cell (FBC) memory device during writing. The FBC memory 40 includes a hole 41, an electron 42, a p-type substrate 43, an insulating layer 44, a depletion region 45, a pinch-off region 46, a first gate G1, a second gate G2, a first source S1 and a first drain D1. The first source S1 and the second gate G2 are connected to the ground (0 V).
For example, during writing of the n-type MOSFET FBC memory 40, a first gate voltage VG1 is applied to the first gate G1, and a first drain voltage VD1 is applied to the first drain D1. When the first gate voltage VG1 is larger than a threshold voltage VT (VT is a positive voltage for an n-type MOSFET) and the first drain voltage VD1 is larger than the first gate voltage VG1, the pinch-off region 46 is formed in the depletion region 45. At this time, the impact ionization leads to the electron-hole pairs generating near the junction of the first drain D1 and the first gate G1. The electrons 42 drift from the pinch-off region 46 into the first drain D1 due to the high electric field. The holes 41 drift and diffuse into the first p-type substrate 43 (floating body). This increases the amount of holes 41 in the floating body, and thus reduces the threshold voltage VT and increases the current from the first drain D1 to the first source S1. Hence, the current from the first drain D1 to the first source S1 can be adjusted through the increment of holes 41 in the first p-type substrate 43.
Please refer to FIG. 3(b), which shows the FBC memory device during reading. During reading of the FBC memory 40, the first gate voltage VG1 is applied to the first gate G1, and the first drain voltage VD1 is applied to the first drain D1. When the first gate voltage VG1 is larger than the threshold voltage VT and the first drain voltage VD1 is smaller than the first gate voltage VG1, an inversion region 47 is formed in the active region 45. At this time, since the first drain D1 collects the electrons 42, the magnitude of the drain current is modulated by the body effect that can indicate the amount of holes 41 storing in the substrate. This different current state can be used for representing a logical state.
Please refer to FIG. 3(c), which shows the floating-body capacitor of the FBC memory device. The disadvantage of the FBC memory device 60 is the leakage current of the floating-body capacitor 48 and source S1. This junction is forward that causes the holes 41 to flow through the floating body capacitor 48 to the source S1. This significantly shortens the data retention time (0.1 second). Therefore, the FBC memory device 60 needs to be refreshed periodically, and thus the power consumption thereof is increased.
In order to overcome the drawbacks in the prior art, a memory formed by using defects is provided. The particular design in the present invention not only solves the problems described above, but also is easy to be implemented. Thus, the present invention has the utility for the industry.